Design methodologies for implementing digital systems in programmable logic. Covers topics related to the design, implementation, and testing of programmable logic devices. Students are introduced to the Very-High-Speed Hardware Description Language (VHDL) entry language and simulation procedures, along with common logic synthesis tools. Programmable logic families, device architectures, and testing procedures are covered in detail. Laboratory exercises lead the student through the complete programmable logic design cycle. Each student is required to prototype a digital system starting with VHDL entry, functional and timing simulations, logic synthesis, device programming, logic probing, and systems verification. Prereq: ECE 562. Lab.