EE 273 - Logic Verification with UVM

Description
EE273 covers non-design System Verilog and Universal Verification Methodology (UVM). It introduces logic verification methodologies and techniques. No prior object oriented programming is assumed. UVM is practiced on sample designs in lab projects with industrial simulation tools.
Credits
3
Attributes
Not a Service Learning Course
Recent Professors
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Recent Semesters
Fall 2019, Spring 2019
Offered
MW, TuTh
Avg. Class Size
60
Avg. Sections
1