EE 272 - SoC Design & Verifi. with System Verilog

Description
The course covers topics in System-on-Chip design and verification with SystemVerilog. Major topics include top-down SoC design; design metrics, techniques, and system-level synthesis; IP integration and system-level verification; SystemVerilog design hierarchy, data types, assertions, interfaces, verification constructs, and testbench structures. Prerequisite: EE 271 or instructor consent.
Credits
3
Attributes
Not a Service Learning Course
Recent Professors
Open Seat Checker
Schedule Planner
Recent Semesters
Fall 2019, Fall 2018, Spring 2018, Fall 2017
Offered
TuTh, MW
Avg. Class Size
60
Avg. Sections
1