Instruction set architecture. Pipelining, vector processors, cache memory, high bandwidth memory design, virtual memory, input and output. Benchmarking techniques. New developments related to single CPU systems. Prerequisites: (ECE 303 and ECE 313 and ECE 320 and ECE 331 and ECE 366 and (ECE 390 or concurrently)) or ((CSE 410 and (ECE 390 or concurrently)) and completion of Tier I writing requirement). Fall of every year, Spring of every year.